The present invention relates to a system for writing data to a memory subsystem in a computer system. More particularly, the present invention relates to a memory controller which provides error correction code (ECC) and data streaming compatibility and control.
A computer system typically includes a microprocessor and a number of subsystems. Examples of subsystems used in a computer system include a memory subsystem and an input/output (I/O) bus subsystem. The memory subsystem commonly includes a block of dynamic random access memory (DRAM) devices. The block of DRAMs stores a wide variety of information used to support the computer system.
The I/O bus system includes an I/O bus which provides the processor with access to other devices external to the computer system such as memory devices, slave-type devices, or other processors. One typical I/O bus is the Micro Channel bus manufactured by International Business Machines Corp. of Armonk, N.Y.
In addition to the memory subsystem and the I/O bus subsystem, a computer system also typically includes some type of processor interface between the microprocessor and the subsystems. The interface provides communication between the processor and the various subsystems in the computer system. In the case of a computer system having a memory subsystem and an I/O bus subsystem, the interface provides communication between the processor and the I/O bus, as well as between the processor and memory devices in the memory subsystem.
Such interfaces typically include bus controller circuitry for acquiring control of the I/O bus, and for providing timing control between the I/O bus and the processor. The bus controller circuitry receives processor request signals from the processor such as command signals, address signals and data signals which represent a requested I/O bus operation. The bus controller circuitry then controls the I/O bus in accordance with those processor request signals to accomplish the requested operation.
The interface also typically includes a memory controller which provides timing control between the processor and the memory devices, as well as between the I/O bus and the memory devices. The memory controller receives request signals from either the processor or the I/O bus, such as command signals, address signals and data signals which represent a requested memory operation. The memory controller then controls the memory devices based on those request signals to accomplish the requested operation.
Two techniques have evolved in the computer industry which are very desirable. The first is the technique of implementing error correction code (ECC) into the data written to and read from memory devices in the computer system. ECC information is used to detect and correct errors in information recovered from a memory device. The ECC information is generated based upon the data word to be stored in the memory device and based upon the particular code being used. Once generated, the ECC information is appended to the data word to be stored, and the entire word, including the ECC information, is written to the memory device. Upon recovery of the information from the memory device, the ECC information is recovered and decoded. Based upon the decoded ECC information, the computer system can determine whether the data word recovered from the memory device contains an error. In certain cases, with the use of certain known ECC techniques, the computer system can not only determine whether an error has occurred in recovering the data word, but the computer system can also regenerate the proper information to correct the data word.
The use of ECC information does, however, present certain problems. The generation and decoding of ECC information is quite cumbersome and time consuming. This slows down the data transfer rate achievable by computer systems implementing ECC techniques. This slow-down is largely attributable to the read-modify-write scheme which must be utilized in writing information using ECC techniques. For example, if one desires to write to one single byte of memory (DRAM) which is accessed in multiple byte segments, several memory accesses are required. First, the data which is already written in the multiple byte memory segment must be read. Then, the particular byte of the multiple byte segment which is to be rewritten must be modified to include the new byte of information. Then, new ECC information must be generated for the new multiple byte data word. Finally, the new multiple byte data word, along with the new ECC information, must be rewritten to the memory device at the desired location. Thus, each write requires two memory accesses (i.e., a read and a write). This results in slower memory transfer times.
In the past, byte-based ECC techniques have been used to increase performance of memory devices. By basing the ECC information on a byte-sized portion of data, the read-modify-write technique is avoided. However, this approach is very expensive due to the increased memory required for the extra ECC information, and due to the need for nonstandard single in-line memory modules (SIMMS) in such a system.
Not only is it desirable to have a computer system which supports ECC techniques, it is also desirable to have a computer system which supports a technique known as data streaming. Data streaming is a technique which provides for mass memory transfers to and from the DRAMs in a computer system via the I/O bus. In Micro Channel Architecture, a starting address and a data STROBE signal are provided by the bus master controlling the Micro Channel bus. The starting address indicates the location at which the mass memory transfer is to begin. The STROBE signal occurs once every 100 nanoseconds and indicates that a 32 bit data word provided by the I/O Micro Channel bus is valid. Thus, current Micro Channel technology provides an I/O bus which can transfer data at a rate of 32 bits every 100 nanoseconds. This type of data streaming requires memory which can be configured for fast transfer rates.
Today's DRAMs are also capable of running in what is referred to as "page mode." Page mode is a fast memory transfer for a large segment of data. One page mode memory access can typically be completed within 100 nanoseconds. In page mode, the row address select (RAS) input to the DRAMs is held active while the column address select (CAS) for the DRAMs is used to clock the proper address into the memory. Since the amount of set-up time required between CAS signals is relatively short, a memory transfer which involves consecutive memory segments can be accomplished quickly using DRAMs operating in page mode.
A problem arises when trying to provide a computer system which utilizes the desirable techniques of ECC and data streaming. Data streaming requires memory devices with fast access times while ECC techniques are slow and cumbersome and require multiple memory accesses for each memory write.